DFT Analyzer™

DFT Analyzer, the industry’s first and only JTAG design-for-test tool, makes every design engineer an expert in boundary scan. Instead of waiting for prototypes to see if JTAG was designed in properly, the rules-based DFT Analyzer gets involved early, during the schematic stage. Later, it examines your CAD files and alerts you to problems with the embedded JTAG infrastructure while there’s still time to make changes without it costing an arm and a leg.

 

Why would you risk the schedule, product quality and manufacturability of any design?

 

After guiding designers through the early phases of JTAG development, DFT Analyzer determines a design’s boundary-scan test coverage and recommends changes to increase coverage. DFT Analyzer is a standalone tool, although its output, consisting of a boundary-scan description of a design, can be imported directly into ScanWorks, our JTAG test system. Once this description is in ScanWorks a set of boundary-scan tests can be automatically generated with minimal effort. In addition, existing ScanWorks projects can be imported into DFT Analyzer to determine where and how test coverage could be improved.

 

 

                   

 

DFT Analyzer is made up of three tools which are employed at different stages in product development. First, as schematics are being developed, DFT Analyzer’s automated Checklist queries a designer or test engineer about the testability features included in a design. These questions are based on sound DFT principles derived by ASSET from its many years of working with board designers to optimize boundary-scan test coverage. In addition, design practices specific to the organization can be included in the Checklist to ensure consistency across all of a company’s designs.

 

Next, DFT Analyzer’s Design Validation tool can be launched after computer aided design (CAD) information has been compiled. With the CAD data that is imported into DFT Analyzer, the Design Validation tool determines whether any pre-established DFT rules have been broken or overlooked. The tool recommends solutions if it encounters a broken rule. Company-specific DFT rules can be added to those already included in DFT Analyzer. New rules are defined in C# programs.

 

DFT Analyzer’s third tool, Test Coverage Analysis, is engaged during the final stages of design before first prototypes of the board are manufactured. This tool determines the extent of boundary-scan test coverage when certain types of tests, such as interconnect, memory and others, are run on the circuit board. In addition, the report contains information concerning which ICT test points can be eliminated by substituting a boundary-scan test for the ICT process. Eliminating ICT test points saves board space and reduces the complexity and cost of ICT test fixtures. In addition, the Test Coverage Analysis module can output results to the DFT Analyzer’s design browser which graphically displays the available test coverage in a schematic view.

 

The final output of DFT Analyzer is a complete boundary-scan description of the design that can be imported directly into the ScanWorks test-generation engine. A comprehensive suite of boundary-scan tests can then be generated and optimized for the first prototype boards. Subsequently, this JTAG test suite can be re-used through the manufacturing process as well as system test and field support.